W02 Heterogeneous Integration: from advanced 3D technology to innovative computing architectures

Start

Tue, 1 Apr 2025 08:30

End

Tue, 1 Apr 2025 12:30

Room

St Clair 2

General Co-Chair

Pascal Vivet, CEA-LIST, France

Workshop Handouts

The workshop description and detailed program is now available, with abstracts and bios, see text below and link above

Workshop Description

3D technologies are becoming more and more pervasive in digital architectures, as a strong enabler for heterogeneous integration. With the limits of current sub-nanometric technologies, 3D integration technology is paving the way to a wide architecture scope, with reduced cost, reduced form factor, increased energy efficiency, allowing a wide variety of heterogeneous architectures. Due to the high amount of required data and associated memory capacity, ML and AI accelerator could benefit of 3D integration not only for HPC, but also for the edge and embedded HPC. 3D integration and associated architectures are opening a wide spectrum of system solutions, from chiplet-based partitioning for High Performance Computing to various sensors such as fully integrated image sensors embedding AI features, but also but also for next generation of computing architectures: AI accelerators, InMemoryComputing, Quantum, etc.

The goal of the 3D Integration Workshop is to bring together experts from both academia and industry, interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.

This half-day event consists of a plenary keynote, invited talks, and a panel.

Workshop Committee

Pascal Vivet, CEA-List, FR, Co-general Chair
Dragomir Milojevic, IMEC/ULB, BE, Co-general Chair
Gianna Paulin, AXELERA AI, CH, Co-program Chair
Peter Ramm, Fraunhofer EMFT, DE, Co-program Chair

Technical Program

8:30 : Workshop opening

8:30 - 9:00 : Keynote

Session Chair : Pascal Vivet, CEA-Leti, FR

“Status of High-End Performance Packaging (2.5D & 3D) - Technology and Market Trends”

Stefan Chitoraga, Yole Group, France

9:00 - 10:00 : Session 1 : Chiplet and 3D solutions for Automotive, Space and AR/VR applications

Session Chair : Gianna Paulin, Axelera AI, CH

“Challenges of future automotive electronics and solutions for the early evaluation of chiplet-based system concepts”, Peter Schneider, Fraunhofer IIS & TU Dresden, DE
“3D/2.5D Heterogeneous Circuits for Space and Automotive”, Fady Abouzeid, STMicroelectronics, FR
“Advancing Space Electronics with Chiplet-Based Architectures”, Denis Dutoit, CEA-List, FR
“Opportunities for 3D Integration to Enable Augmented Reality Glasses”, Tony WU, META, USA

10:00 - 11:00 : Coffee Break

11:00 - 12:00 : Session 2 : Advanced system integration for Quantum processors, and Innovative 3D Design Flows

Session Chair : Peter Ramm, Fraunhofer EMFT, DE

“Heterogeneous integration technology in large-scale trapped ion quantum processors”, Bassem Badawi, University of Innsbruck, AT
“3D implementation flows for multi-die Logic-on-Logic & CMOS2.0”, Dragomir Milojevic, Univ ULB & IMEC, BE
“Addressing Thermal and Stress Effects in 3D ICs”, Nermeen Hossan, SIEMENS EDA, Egypt
“PPAT assessment for multi-core SOC in 2D and 3D using electro-thermal co-simulation flow”, Selim Abou Samra, CADENCE, FR

12:00 - 12:30 : PANEL

« Heterogeneous Integration for an open European Chiplet Ecosystem »

Panel chairs : Pascal Vivet, Gianna Paulin

Panelists :