Compared to software design, hardware design is more expensive and time-consuming. This is partly because software community has developed a rich set of modern tools to help software programmers to get projects started and iterated easily and quickly. However, the tools are seriously antiquated and lacking for hardware design. Modern digital chips are still designed manually using hardware description language such as Verilog or VHDL, which requires low-level and tedious programming, debugging, and tuning. In this tutorial, we will introduce Agile Hardware Specialization (AHS) : A toolbox for Agile Chip Front-end Design.

The tutorial will highlight the methodology and open source tools in AHS for both chip design and verification. From the design perspective, AHS present three ways that use different programming interfaces and target different scenarios, including; 1) a multi-level hardware intermediate representation based high-level synthesis flow, which uses C and C++ as the programming language; 2) an embedded hardware description language, which uses Rust as the programming language; 3) a large language model (LLM)-powered hardware design flow, which uses natural language as the programming language. These three different methodologies exhibit different trade-offs in productivity and PPA (performance, power, and area) for chip design. From the verification perspective, we will present agile simulation and debugging tools, which can check the functional and performance behaviors of the hardware. The attendees will learn the methodology, design automation fundamentals, and software tools of AHS.

Speakers

Dr. Yun Liang, Professor, Peking University, China
Xiaochen Hao, Ph.D Candidate, Peking University, China

Target Audience

We invite DATE 2025 participants with a keen interest in chip design and verification and computer-aided design (CAD) tools. Please join us!

Required Background

•     Basic knowledge of programming such as C  or C++
•     A keen interest in learning hardware specialization and Electronic Design Automation (EDA)
•     Desirable: prior knowledge of high level synthesis and associated tool-chains.

Detailed Program

•     Part 1: Lecture (45 mins)
•     Part 2: Hands-on session (45 mins)